1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device using a SOI(silicon on insulator) wafer, and more particularly to a method for fabricating a CMOS device capable of increasing hole mobility in a PMOS device.
2. Description of the Related Art
Due to the fast development in semiconductor device industry, a semiconductor device using the SOI wafer instead of a single crystalline silicon wafer made of bulk silicon, has been proposed. A semiconductor device formed in the SOI wafer (hereinafter, SOI device) compared to that formed in the single crystalline silicon wafer, has advantages that a high speed due to a low junction capacitance, and driving voltage in reduction due to a low threshold voltage and latch-up prevention due to a complete isolation.
The SOI wafer has a stack structure of a base substrate as a means for supporting, a buried oxide layer disposed on the base substrate, and a semiconductor layer in which a device is formed and disposed on the buried oxide layer. Herein, the semiconductor layer should have a uniform thickness and more preferably has a thickness below 100 nm so that the device formed in the SOI wafer has the foregoing advantages.
On the other hand, in the CMOS device that is comprised of a NMOS device and a PMOS device, the hole mobility in the PMOS device is generally lower than the electron mobility in the NMOS device. That means, the CMOS device formed in the SOI wafer may not have good property owing to the PMOS device having relatively poor carrier mobility. Accordingly, it should be required to increase the hole mobility in the PMOS device in order for the CMOS formed in the SOI wafer to have good property.
There is taught in IEEE trans. Electron Device, vol., 39, p. 2665,1992, M. Roser, S. R. Clayton, P. R. de la Houssaye and G. A. Garcia, Hole-mobility in fully depleted thin-layer SOS MOSFETs that the hole mobility is increased when the compressive which is a stress type existing in the semiconductor layer of the CMOS formed on the SOI wafer.
FIG. 1 is a graph showing the hole mobility vs. the gate voltage based on the compressive stress applied to the semiconductor layer in the PMOS transistor formed on the SOI wafer. In the drawing, A signifies the case where the compressive stress within the semiconductor layer is relatively small and B signifies the case where the compressive stress within the semiconductor layer is relatively great.
As shown in the drawing, the maximum hole mobility is obtained at gate voltage of -1.0V when the compressive stress in the semiconductor layer is great, i.e. in case of B. As a result, it is obvious that the hole mobility is increased when the compressive stress in the semiconductor layer is great.
Therefore, it is required to increase the hole mobility in the PMOS device so as to improve the property of CMOS device formed in the SOI wafer, and the semiconductor layer acting as a body in the PMOS device should be affected by the compressive stress so as to increase the hole mobility in the PMOS device.